[問題] 請教VHDL裡always的問題
程式碼:
module TEST( y, reset, clk );
output y;
input reset, clk;
reg c;
assign y = c;
always @( reset or clk )
begin
if( reset )
c = 4'b0;
else if( clk )
c = 4'b1;
end
endmodule
而跑出來的結果:http://images.plurk.com/1e341f7e72261158f38e7d4e9af0d46f.jpg
我的問題是: 在2ns的地方，clk為0 且 reset為0，照理說y的值應該不會變呀?!?!
可是結果卻是y變1
請高手幫忙解答，謝謝。
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◆ From: 140.138.224.111
※ 編輯: rocmewtwo 來自: 140.138.224.111 (04/15 18:51)
※ 編輯: rocmewtwo 來自: 140.138.224.111 (04/15 18:53)
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※ 編輯: rocmewtwo 來自: 140.138.224.111 (04/16 01:19)
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