[問題] VHDL的問題
請問要怎麼將下面的程式改寫成可以累加的呢
http://www.pixnet.net/photo/z701660993/74075903
如上圖 當我輸入是"100"時 輸出會是15
我希望能將它變成15=>30=>45 這樣一直加上去
而當輸入變成"000"時 輸出則會維持45這個數值 而不是歸零
希望有人能幫幫我這新手的問題QQ
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity A1 is
port(
I : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
C : OUT integer range 99 downto -99);
END A1;
ARCHITECTURE A OF A1 IS
BEGIN
PROCESS(I)
variable counter : integer range -99 to 99;
BEGIN
counter := 0;
if I = 000 then counter := counter+0;
elsif I = 001 then counter := counter+1;
elsif I = 010 then counter := counter+5;
elsif I = 011 then counter := counter+10;
elsif I = 100 then counter := counter+15;
elsif I = 101 then counter := counter-10;
elsif I = 110 then counter := counter-5;
elsif I = 111 then counter := counter-1;
end if;
C<=counter;
END PROCESS;
END A;
--
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