[閒聊] 記憶體幾個簡單的參數定義

看板PC_Shopping (個人電腦購買)作者justice2008 (搶錢搶糧搶娘們)時間16年前 (2009/04/13 04:58)推噓13(13推 0噓 2→)

留言15則, 15人參與討論串1/1

板上常常講4-4-4-10 5-5-5-15 這類的一堆數字這些各代表啥意思勒小弟稍微解釋一下希望可以釣到大魚XD 所謂的4-4-4-10代表4(tCL)-4(tRCD)-4(tRP)-10(tRAS) tCL:CAS Latency (Time) CAS全名是Column Address Strobe 翻做行位址控制器 Latency字典查的到這理翻做延遲 Time....不用解釋了吧= = 整句的意思是行位址控制器延遲(時間) tRCD:DRAM RAS# to CAS# Delay (Time) RAS全名是Row Adress Strobe 翻做列位址控制器 CAS看前面 Delay翻做延遲整句的意思是列位址控制器至行位址控制器的延遲時間 tRP:DEAM RAS# Precharge RAS看前面 Precharge這邊翻做預充電整句翻做列位址控制器的預先充電 tRAS:Row Active Time(Active to Prechareg Delay) 整句翻做列動態時間其實這東西看主機板的說明書通常是會解釋啦.... 至少我手上這本技嘉的說明書有解釋後面還有一大串參數(大約七個左右) 普通的User大致會玩的是前面這四個後面的我就不一一介紹了orz 這些參數其實是有公式可以算出理論效能就是了.... 如果有人想知道詳盡的解釋可以看下面的參考資料我就懶的翻譯了orz 有心看的自己去研究吧 ----------------------------------------------------------------------------- tCAS The number of clock cycles needed to access a certain column of Data in SDRAM. CAS Latency, or simply CAS, is known as Column Address Strobe Latency, sometimes referred to as tCL. tRCD (RAS to CAS Delay) The number of Clock cycles needed between a Row Address Strobe (RAS) and a CAS. It is the time required between the computer defining the row and column of the given memory block and the actual read or write to that location. Stands for Row address to Column address Delay. tRP (RAS Precharge) The number of clock cycles needed to terminate access to an open row of memory, and open access to the next row. Stands for Row precharge time. tRAS The minimum number of clock cycles needed to access a certain row of data in RAM between the data request and the precharge command. Known as Active to Precharge Delay. According to Mushkin, in practice for DDR SDRAM, this should be set to at least tRCD + tCAS + 2 to allow enough time for data to be streamed out ----------------------------------------------------------------------------- 來源:wiki英文版連結:http://en.wikipedia.org/wiki/SDRAM_latency -- 今天有人丟水球問這個東西啦.... 不過我剛剛在看動畫我只是把答應的東西丟上來做解釋而已希望大家能看的懂orz 我應該寫的夠淺了吧 -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 61.217.211.226