Re: [問題] 這裡適合問嗎?
※ 引述《garsam (鴨子)》之銘言：
: error:verilog HDL syntax error:ignored non-printable character 'h1
: verilog的..
: 在compile時出現這句...可是找不出來錯誤><
: 誰知道這句什麼意思啊~"~
module carty(Q,CO,CLK,Count,Load,D);
output [3:0] Q;
output CO;
input [3:0] D;
input Count,Load,CLK;
wire c1,c2,c3,c4,c5,c6,c7,c8,a1,a2,a3,a4,a5,b1,b2,b3,b4,b5,b6,b7,b8,b9,e1,e2,e3;
JK J1(Q[0],CLK,c1,c2);
JK J2(Q[1],CLK,c3,c4);
JK J3(Q[2],CLK,c5,c6);
JK J4(Q[3],CLK,c7,c8);
not (a1,Load);
not (a2,D[0]);
not (a3,D[1]);
not (a4,D[2]);
not (a5,D[3]);
and (b1,Count,a1);
and (b2,D[0],Load);
and (b3,a2,Load);
and (b4,D[1],Load);
and (b5,a3,Load);
and (b6,D[2],Load);
and (b7,a4,Load);
and (b9,a5,Load);
and (e1,b1,Q[0]);
and (e2,b10,Q[1]);
and (e3,b11,Q[2]);
and (CO,b12,Q[3]);
or (c1,b1,b2);
or (c2,b1,b3);
or (c3,e1,b4);
or (c4,e1,b5);
or (c5,e2,b6);
or (c6,e2,b7);
or (c7,e3,b8);
or (c8,e3,b9);
endmodule
module JK(Q,CLK,J,K);
output Q;
input CLK,J,K;
reg Q;
always @(posedge CLK)
case ({J,K})
2'b00:Q=Q;
2'b01:Q=1'b0;
2'b10:Q=1'b1;
2'b11:Q=~Q;
endcase
endmodule
and (b8,D[3],Load);
這個東西^^"
--
※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 59.104.20.223
推
61.229.37.164 04/11, , 1F
61.229.37.164 04/11, 1F
討論串 (同標題文章)
MacDev 近期熱門文章
PTT數位生活區 即時熱門文章
