[問題] 請問VHDL程式相關問題!!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity music is
port(
clk : in std_logic;
sel : in std_logic_vector(1 downto 0);
music_out : out std_logic
);
end music;
architecture arch of music is
component clk_div_music
generic(divisor:integer:=8);
port(
clk_in : in std_logic;
clk_out: out std_logic
);
end component;
signal clk1,clk2: std_logic;
begin
u1: clk_div_music
generic map(7045) --Do 261.6Hz 1.8432M->7045
port map(clk,clk1);
u2: clk_div_music
generic map<6275) --Rai 293.7Hz 1.8432M->6275
port map(clk,clk2);
---------- process ---------
process (clk1,clk2)
begin
------------------------------------------------------------
這段如何寫出重複執行 Do 和 Rai 的音?(除頻器的程式碼已匯入)
謝謝幫忙!!!
-------------------------------------------------------------
end process;
end arch;
--
--
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