[問題] VHDL的錯誤問題
剛剛再跑VHDL時
從範例抄下的題目
跑的時候出現一個錯誤
Error (10500): VHDL syntax error at test.vhd(7) near text "END"; expecting
an identifier ("end" is a reserved keyword), or "constant", or "file", or
"signal", or "variable"
原始程式碼是
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--Simple module that connects the SW switches to the LEDR lights
ENTITY part1 IS
PORT (SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);--red LEDs
END part1;
ARCHITECTURE Behavior OF part1 IS
BEGIN
LEDR <= SW;
END Behavior;
請各位大大
幫我檢查一下
到底是什麼問題
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